Staff Engineer - Analog Layout
Core
Lead full-custom layout for complex Analog / Mixed-Signal IP blocks including bandgap references, LDOs, charge pumps, PLLs, and temperature sensors, ensuring quality from floor-planning to tape-out.
Role type
Staff Engineer - Analog Layout
Builds
Analog and Mixed-Signal IP blocks for memory and storage solutions
Domain
Semiconductor manufacturing, advanced nodes (FinFET 3nm/5nm, planar CMOS)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
full-custom layout, floor-planning, device matching, noise isolation, substrate strategies, power/ground planning, DRC/LVS/ERC signoff, foundry PDK expertise, layout-dependent effects (LDEs), mentorship, IP reuse, methodology development
Preferred skills
FinFET node expertise (TSMC 3nm, 5nm), multi-Vt/multi-fin strategies, advanced metal stack planning, legacy IP support
Technologies
TSMC 3nm, 5nm, 40nm, 65nm, 90nm, FinFET, planar CMOS
Responsibilities
Lead full-custom layout for complex Analog / Mixed-Signal IP blocks; Own layout quality from floor-planning to tape-out; Work closely with circuit designers to translate performance goals into layout strategies; Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks; Provide technical guidance and design reviews for junior and mid-level layout engineers; Establish and document best-known methods (BKMs) for AMS layout across nodes
Seniority
Staff, hands-on IC with mentorship
