Staff/Principal Engineer. ASIC Design Verification (DDR expert)
Core
End-to-end ownership of DDR interface verification for complex SoC components, ensuring best-in-class quality from concept through production.
Role type
Staff/Principal ASIC SoC Design Verification Engineer (DDR expert)
Builds
Foundational technologies for advanced memory and computing systems
Domain
Semiconductor / Hardware Design / Memory Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DDR verification, SoC verification, C/C++ test development, RTL simulation, netlist simulation, emulation platforms, DDR5/DDR6/LPDDR6 expertise
Preferred skills
Advanced verification methodologies, PCIe/NVMe/NAND sub-systems, Gen-AI tools for verification, comprehensive test plan design
Technologies
C, C++, RTL, netlist, emulation platforms, DDR5, DDR6, LPDDR6
Responsibilities
Own DDR interface verification from concept through post-silicon bring-up and production support; Define DDR test requirements with architecture, firmware, and design teams; Create sub-system and SoC-level verification test plans; Develop and debug SoC verification firmware and tests in C; Support verification across RTL, netlist simulation, and emulation platforms
Seniority
Staff/Principal, hands-on IC
