Principal Engineer, ASIC Pre Silicon Validation (HAPS Prototyping/Emulation)
Core
Lead pre-silicon validation and prototyping of System-on-Chip (SoC) designs using Xilinx HAPS emulation platforms to verify hardware, RTL, and firmware integration before silicon fabrication.
Role type
Principal Engineer, ASIC Pre Silicon Validation (HAPS Prototyping/Emulation)
Builds
Pre-silicon SoC prototypes and emulation environments for memory and storage controllers
Domain
Semiconductor hardware design, FPGA emulation, memory/storage interfaces (PCIe, NVMe, LPDDR, ONFI)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Xilinx Vivado Flow, HAPS platform implementation (HAPS80/HAPS100), SoC verification planning, Verilog RTL coding, VCS simulation and debugging, Python/Perl/TCL scripting, root-cause analysis across hardware and RTL layers
Preferred skills
Xilinx Ultrascale FPGA expertise, Protocompiler Tool flow, PCIe/NVME/LPDDR/ONFI architecture knowledge, AXI interface knowledge
Technologies
Xilinx Vivado, HAPS, VCS, Protocompiler, Chipscope, Python, Perl, TCL
Responsibilities
Complete Xilinx FPGA and Protocompiler tool flows; own full SOC deployment on HAPS platforms; collaborate with Design/SOC/C/FW teams to plan and execute validation; review and create validation plans for PCIe/LPDDR/ONFI subsystems; perform processor-based SoC prototyping and emulation; run SOC C-based simulations for test case understanding and debug; write Verilog RTL when required; debug PCIe/LP bring-up with overseas teams
Seniority
Principal, hands-on IC
