HIG-HBM ENGINEERING MANAGER - LAYOUT
Core
Lead a distributed team developing complex analog, mixed-signal, and custom layouts for next-generation AI and high-performance computing solutions.
Role type
Senior IC Layout Design Engineering Manager
Builds
Block-level and full-chip layouts for analog circuits, mixed-signal components, and custom IP blocks
Domain
Semiconductor manufacturing, Advanced CMOS technology (Planar, FinFET), High Bandwidth Memory (HBM)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design in advanced CMOS nodes, Team management (5+ years), LVS/DRC verification, Project planning and scheduling, Mentorship, Critical IP block expertise (PLL, ADC, DAC, bandgap, etc.), Physical design fundamentals (matching, electromigration, IR drop, etc.), Tapeout support
Preferred skills
HBM or high-performance computing product experience, Advanced physical design methodologies, Scripting (Python, SKILL, Tcl)
Technologies
Cadence VLE/VXL, Mentor Graphics Calibre DRC/LVS
Responsibilities
Manage team crafting critical layouts for analog/mixed-signal/custom blocks, Oversee layout verification (LVS, DRC, Antenna), Ensure timely delivery of block-level layouts, Coordinate planning and scheduling for concurrent projects, Mentor layout engineers, Perform detailed reviews of sub-block-level layouts
Seniority
Senior, hands-on IC with management responsibilities
