SMTS Physical Design Engineer
Core
Own the complete back-end implementation of a high-speed interface chip program, driving performance-scaling innovation from synthesis netlist through GDSII tape-out.
Role type
Senior IC physical design engineer (mixed-signal/high-speed interface)
Builds
High-speed interface chips (PHYs) for memory and storage solutions
Domain
Semiconductor / Mixed-signal physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
full-flow physical design, place-and-route, static timing analysis, power distribution network design, DRC/LVS/ERC sign-off, mixed-signal floorplanning, hard macro integration, root-cause analysis
Preferred skills
analog-adjacent chip physical design, high-speed I/O pad ring design, power domain implementation (UPF/CPF), power integrity analysis (Voltus/Redhawk), Synopsys IC Compiler 2 experience
Technologies
Cadence Innovus, Cadence Tempus, Mentor Calibre, Cadence Voltus, Apache Redhawk, Synopsys IC Compiler 2
Responsibilities
Define and implement full chip floorplans with analog block placement and partitioning; Design and implement chip power distribution networks (PDN); Execute full-chip place-and-route; Own static timing analysis across all PVT corners; Perform IR drop and electromigration analysis; Execute DRC, LVS, and ERC sign-off; Implement scan chain insertion and ATPG pattern generation; Interface with foundry on PDK questions and tape-out requirements.
Seniority
Senior, hands-on IC
