HBM Hardware Emulation Architect
Core
Architecting, enabling, and deploying hardware emulation capabilities for next-generation HBM products to support pre-silicon validation and rapid debug.
Role type
Senior IC hardware emulation architect
Builds
Hardware emulation environments, testbenches, transactors, and verification IP for complex SoCs and subsystems
Domain
Semiconductor / High Bandwidth Memory (HBM) / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL design and debug, hardware emulation platforms, SoC architecture, interconnects, IP integration, firmware/hardware interaction, large-scale design debugging, hybrid validation flows
Preferred skills
Hands-on experience with hardware emulation platforms, full-chip or subsystem level debugging, low-level software interaction
Technologies
Palladium, Veloce, Zebu
Responsibilities
Develop and maintain hardware emulation environments for complex SoCs and subsystems; Compile, configure, and debug large-scale RTL designs on emulation platforms; Support pre-silicon validation, firmware bring-up, and early software development using emulation; Debug functional, performance, and connectivity issues across RTL, firmware, and system layers; Create emulation testbenches, transactors, and models for system-level use cases; Enable hybrid validation flows (simulation + emulation + FPGA prototyping as needed)
Seniority
Senior, hands-on IC
