SENIOR ENGINEER HBM LAYOUT
Core
Design and development of analog, mixed-signal, custom digital blocks and full chip level integration for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Senior IC Layout Design Engineer (Analog/Mixed-Signal)
Builds
Custom analog and mixed-signal blocks (PLL, ADC, DAC, LDO, etc.) and full chip layouts for HBM
Domain
Semiconductor / Memory / Analog & Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design in advanced CMOS, Cadence VLE/VXL, Mentor Calibre DRC/LVS, layout of critical blocks (Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier), Analog Layout fundamentals (Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop), layout effects on circuit performance (speed, capacitance, power, area)
Preferred skills
Tape out support, managing multiple layout projects, physical verification of custom layout
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and development of analog, mixed-signal, custom digital block and full chip level integration support; Perform layout verification like LVS/DRC/Antenna, quality check and documentation; Responsible for on-time delivery of block-level layouts with acceptable quality; Leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones; Effectively communicating with Global engineering teams
Seniority
Senior, hands-on IC
