Sr Staff Analog Layout Engineer
Core
Design and optimize analog mixed-signal layouts (RX, TX, PLL) for High-Speed SerDes IPs, ensuring compliance with design rules and schematics.
Role type
Senior Staff Analog Layout Engineer
Builds
High-Speed SerDes (HSS) IPs for data infrastructure, enterprise, cloud, AI, and carrier architectures
Domain
Semiconductor / Analog Mixed-Signal / High-Speed SerDes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog mixed-signal layout design, Floor planning, Custom layout, DRC/LVS/ANT/LUP/ESD/PERC verification, CAD tools (Cadence Virtuoso, Mentor Graphics, Synopsys Custom Compiler), FinFET process knowledge
Preferred skills
TSMC 5nm/3nm/2nm process knowledge, Mentoring junior engineers
Technologies
Cadence Virtuoso, Mentor Graphics, Synopsys Custom Compiler
Responsibilities
Design and optimize analog mixed-signal layouts, Work closely with circuit designers to meet specifications, Verify layouts against design rules and schematics, Maintain detailed documentation of layout methodologies and verification results
Seniority
Senior Staff, hands-on IC with mentorship responsibilities
