STAFF ENGINEER - HIG HBM PSE
Core
Lead end-to-end validation runs for High Bandwidth Memory (HBM) and DRAM, ensuring on-schedule execution, risk management, and coverage completeness across MBIST and Native flows.
Role type
Staff Engineer, HBM/DRAM Validation & Platform Leadership
Builds
Validation runs, test programs, automation scripts, dashboards, and silicon debug solutions for HBM/DRAM products.
Domain
Semiconductor Manufacturing / Memory Technology (HBM, DRAM, NAND)
Required skills
HBM/DRAM validation, MBIST/Native Mode testing, Verilog simulation, C/C++/Python/APG scripting, data analytics, silicon debug, test platform development
Preferred skills
Linux programming, UVM, lab equipment operation (oscilloscopes, logic analyzers), ML-driven validation workflows, CS/QS shmoo target definition
Technologies
SM3/Cobra, Advantest V93K, Verilog, C, C++, Python, APG, Confluence, Jira, Git, Perforce
Responsibilities
Lead end-to-end Validation Run execution; Develop and debug test programs on SM3/Cobra and Advantest V93K; Perform power/thermal characterization and Verilog simulations; Lead silicon debug across Design, Verification, Quality, and System Engineering; Coach junior engineers on validation best practices.
Seniority
Staff, hands-on IC with mentorship
