ASIC Design Engineer - Performance Monitoring
Core
Design and implement RTL features and system-level IP for high-performance GPUs/SOCs, focusing on performance monitoring methodologies.
Role type
Senior IC ASIC Design Engineer (Performance Monitoring)
Builds
System-level IP and RTL features for industry-leading GPUs/SOCs
Domain
Semiconductor / ASIC Design / GPU Architecture
Required skills
RTL design (Verilog), SOC design flows, design automation, scripting (Perl/Python), debugging, latency analysis, multi-clock domain handling
Preferred skills
AI tools for productivity, design verification tools (VCS, dc_shell)
Technologies
Verilog, Perl, Python, VCS, dc_shell, Debussy, GDB
Responsibilities
Define and develop system-level RTL and performance measurement methodologies; Design and implement RTL features through the full design cycle; Run and debug RTL checks (CDC, RDC, Lint, Synthesis, Logic-Equivalence); Automate flows to support system-level IP; Collaborate with architects, verification, and SW engineers
Seniority
Senior, hands-on IC
