Senior ASIC Design Engineer, GPU Core Pipeline IP
Core
Design and implement control subsystems and micro-architecture for next-generation GPU ASICs, serving consumer graphics, self-driving cars, and AI applications.
Role type
Senior IC ASIC Design Engineer (GPU Core Pipeline IP)
Builds
Graphics and compute features within GPU IP blocks
Domain
Semiconductor / GPU / AI Computing
Deliverable
production ML models
Required skills
RTL design (Verilog/SystemVerilog), Micro-architecture development, Digital design fundamentals, Computer architecture, ASIC design methodologies, Timing closure, Synthesis, DFT, Physical design considerations
Preferred skills
3D graphics processing experience, Processor design experience, C/C++ programming, Scripting (Perl/Python), Debugging skills
Technologies
Verilog, SystemVerilog, C++, Perl, Python
Responsibilities
Develop RTL and collaborate on design specifications, Work with HW architects to make implementation choices, Collaborate with verification engineers for validation, Participate in silicon bring-up and post-silicon debug, Ensure designs meet performance, power, area, and timing goals
Seniority
Senior, hands-on IC
