ASIC CAD Engineer, Clocks Methodology
Core
Develop and validate clocking methodology solutions and custom CAD tools for next-generation heterogeneous chip designs.
Role type
Senior IC ASIC CAD Engineer (Clocks Methodology)
Builds
Scalable clocking validation tools, automation frameworks, and quality check infrastructure for SoCs, CPUs, GPUs, and Networking products.
Domain
Semiconductor hardware design, VLSI, clocking methodologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital logic design, computer architecture, C/C++ programming, scripting (Python, Perl, Tcl), CAD tool development, engineering automation, algorithm design, data structures, software design principles
Preferred skills
VLSI design flows, clocking methodologies, physical design, building tools for hardware engineering teams
Technologies
C++, Python, Perl, Tcl, NVIDIA internal compilers, CAD infrastructure
Responsibilities
Own validation of clocking methodology solutions across multiple product lines, develop robust validation strategies and automation, solve complex engineering problems with scalable solutions, partner with design and architecture teams, collaborate with QA for production-ready releases, work with global engineering teams
Seniority
Senior, hands-on IC
