Senior Mask Layout Design Engineer
Core
Performing physical layout for high-speed mixed-signal circuits (PLLs, SerDes, ADCs, ESD) in sub-micron CMOS technologies.
Role type
Senior IC mask layout design engineer
Builds
High-speed mixed-signal circuit layouts for VLSI products
Domain
Semiconductor / Analog IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Mixed-signal circuit layout, sub-micron CMOS technology, Cadence Virtuoso, DRC/LVS flows, Perl/Python scripting, verification tools (Dracula, Hercules, Calibre, Primeyield)
Preferred skills
Cross-functional collaboration, team optimization
Technologies
Cadence Virtuoso, Dracula, Hercules, Calibre, Primeyield, Perl, Python
Responsibilities
Perform physical layout for mixed-signal functions, customize designs for VLSI integration, floor plan and verify against design rules and schematics
Seniority
Senior, hands-on IC
