Physical Design Power Optimization and Modeling Engineer
Core
Physical Design Power Optimization and Modeling for high-speed communication chips, focusing on RTL2GDS flow, power/clock distribution, place & route, timing closure, and noise fixes.
Role type
Senior IC physical design power engineer
Builds
Networking silicon chips for high throughput and low latency
Domain
Semiconductor / Networking / Physical Design
Deliverable
production ML models | product features
Required skills
Physical design flow (RTL2GDS), Power optimization, Power estimation, Power modeling, Synthesis, Place and route, Timing closure, Noise analysis, EDA tools (Synopsys, Cadence), AI tools for engineering workflows
Preferred skills
Physical verification, PNR, STA, FE design experience
Technologies
Synopsys, Cadence
Responsibilities
Optimize power across blocks/top-level/fc under challenging constraints; Execute synthesis, power/clock distribution, place & route, timing closure, and power/noise fixes; Perform power estimation and modeling.
Seniority
Mid-level, hands-on IC
