Physical Design Power Optimization and Modeling Engineer
Core
Physical Design Power Optimization and Modeling for high-speed communication chips.
Role type
Physical Design Power Engineer
Builds
Networking silicon chips with high throughput and low latency
Domain
Semiconductor / Networking
Required skills
Physical design flow (RTL2GDS), Power optimization, Power estimation, Power modeling, Synthesis, Power and clock distribution, Place and route, Timing closure, Noise fixes, EDA tools (Synopsys, Cadence), AI tools for engineering workflows
Preferred skills
Physical design methodologies (PNR, STA, physical verification), Front-end (FE) design experience
Technologies
Synopsys, Cadence
Responsibilities
Optimize power for blocks/top-level/fc under challenging constraints; Perform synthesis, power/clock distribution, place and route, timing closure, and power/noise fixes; Conduct power estimation and modeling
Seniority
Entry-level to Mid-level, hands-on IC
