NVIDIA 2027 Internships: Hardware Design for Test (DFT)
Core
12-week full-time internship for students pursuing M.S. or Ph.D. in Electrical or Computer Engineering to work on Hardware Design for Test (DFT) projects with measurable business impact.
Role type
Hardware Design for Test (DFT) Intern
Builds
Hardware chips and test architectures for AI, gaming, robotics, and self-driving cars
Domain
Semiconductor hardware design and verification
Deliverable
production ML models
Required skills
Design for Test (DFT), Digital Design, Test Architecture, Static Timing Analysis (STA), Debugging (Pre-Silicon/Post-Silicon), Scan Chain Design, ATPG, Boundary Scan, Memory BIST, Logic BIST, Compression, At-Speed/Delay Testing
Preferred skills
Perl, TCL, C, C++, Python, Synopsys, TetraMAX, Cadence Modus, Linux
Technologies
Synopsys, TetraMAX, Cadence Modus, Linux
Responsibilities
Design and implement DFT strategies, develop test architectures, perform static timing analysis, debug silicon issues, create scan chains and BIST solutions
Seniority
Intern
