Senior ASIC Verification Engineer - HSIO
Core
Verify ASIC design, architecture, golden models, and micro-architecture of High Speed I/O controllers (Ethernet, NVLink) at IP/sub-system levels using advanced DV methodologies.
Role type
Senior IC ASIC verification engineer (HSIO)
Builds
High Speed I/O controllers for SOCs and GPUs
Domain
Semiconductors / High Speed I/O / AI Computing
Required skills
SystemVerilog, UVM, coverage-driven verification, random stimulus, assertion-based verification, debugging, analytical problem solving
Preferred skills
System level architecture of HSIO designs (Ethernet, CXL), Perl/Python scripting, AI-enabled code assist tools
Technologies
UVM, SystemVerilog, Ethernet, NVLink, CXL, Perl, Python
Responsibilities
Build reusable bus functional models, monitors, checkers, and scoreboards; define verification scope and develop test plans/tests; collaborate with architects and designers
Seniority
Senior, hands-on IC
