Senior ASIC Design Engineer - XBAR IP
Core
Designing state-of-the-art memory subsystem components for Graphics Processors, focusing on micro-architecture, RTL implementation, and verification.
Role type
Senior ASIC Design Engineer (Memory Subsystem IP)
Builds
Memory subsystem components for Graphics Processors
Domain
Semiconductor / ASIC Design / Graphics Hardware
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design, Verilog, ASIC design flow, micro-architecture, timing analysis, DFT, logic synthesis, FPGA prototyping
Preferred skills
Memory subsystem or network interconnect IP experience, Python/Perl/shell scripting, team leadership
Technologies
VCS, Debussy, GDB, FPGA
Responsibilities
Own micro-architecture and RTL development of design modules; Micro-architect features to meet performance, power and area requirements; Collaborate with verification teams to verify correctness; Co-operate with timing, VLSI and Physical design teams; Work on post-silicon verification and debug
Seniority
Senior, hands-on IC
