Senior SOC Design Engineer - Networking Group
Core
Design and integrate system-level methodologies, tools, and IPs for next-generation DPUs and Switch Silicon chips, delivering high-efficiency, low-latency high-speed communication devices.
Role type
Senior SOC Design Engineer (Networking)
Builds
DPUs and Switch Silicon chips
Domain
Semiconductor / Networking Chip Design
Required skills
ASIC architecture, Micro-Architecture, RTL design, verification, timing closure, Physical design, SoC development, tape-out experience, cross-functional collaboration, project milestone tracking
Preferred skills
Synthesis, DFT, RTL Build, Design Automation, smartNIC, high-speed interconnects, performance/power/area analysis, Perl/Python scripting
Technologies
Verilog/SV, Cadence, Indago, GDB, C/C++, Python
Responsibilities
Define system-level methodologies and tools to build subsytems efficiently; integrate project pieces and deliver models for verification at cluster/sub-system/SOC/emulation levels; work with SOC Assembly and cross-functional teams to execute milestones; define project milestones based on roadmaps and track them via agile framework.
Seniority
Senior, hands-on IC
