Post-Silicon Validation and Methodology Engineer
Core
Build test infrastructure, characterization methodologies, and coverage strategies to validate next-generation silicon (GPU, SoC, CPU) from first power-on through PVT sign-off, partnering across architecture, firmware, and software teams.
Role type
Senior IC hardware validation and methodology engineer
Builds
Test infrastructure, characterization methodologies, bring-up playbooks, and AI-assisted lab workflows for silicon bring-up and qualification
Domain
Semiconductor hardware engineering (silicon bring-up, validation, debug)
Required skills
Silicon bring-up and validation, root-cause analysis of HW/SW interactions, lab instrumentation (oscilloscopes, logic analyzers, power analyzers), Python/C++ scripting for automation, AI tool proficiency for data analysis and debug triage, digital development fundamentals (timing, clocking, power, noise)
Preferred skills
GPU/SoC architecture bring-up experience, in-system test and DFT feature development, fault modeling, margin test flow design, process redesign for faster debug velocity
Technologies
Python, C/C++, oscilloscopes, logic analyzers, power analyzers, AI tools for log analysis and anomaly detection
Responsibilities
Own bring-up, validation, qualification, and productization plans; build and deploy AI-assisted lab workflows; lead root-cause analysis on HW/SW issues; identify and redesign broken processes in bring-up sequencing and regression frameworks
Seniority
Senior, hands-on IC
