SOC Design Engineer, ASIC Tools and Methodology Development
Core
Develop and deploy in-house tools and workflows to support engineering business units, specifically focusing on verifying common design blocks and automating RTL generation.
Role type
SOC Design Engineer (ASIC Tools and Methodology)
Builds
In-house verification tools, automated RTL generation workflows, and IP development environments
Domain
Semiconductor / ASIC Design / Digital Logic
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog, Python scripting, Perl scripting, Unix/Linux shell scripting, Makefiles, digital design concepts
Preferred skills
ASIC verification, Clocks/Resets design and verification, CDC design/verification flows, backend flows (Synthesis, Timing)
Technologies
Verilog, Python, Perl, Unix/Linux, Makefiles
Responsibilities
Develop and deploy in-house tools and workflows; Take ownership of tools that verify common design blocks; Act as a DevOps engineer for automated RTL generation; Build new workflows and methodologies for IP development environments
Seniority
Mid-level IC Engineer
