MTS, Interface Pathfinding Hardware Development Engineer
Core
Own characterization for a high-speed interface test-chip program, including planning, bench hardware development, measurement automation, and sim-to-silicon correlation.
Role type
Senior IC hardware development engineer (semiconductor characterization)
Builds
High-speed interface test chips and automated characterization infrastructure
Domain
Semiconductor memory and storage, high-speed interfaces, signal integrity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
semiconductor characterization, high-speed time-domain measurement, BERT operation, root cause analysis, instrument automation, PDN measurement, frequency-domain fixture de-embedding, first silicon bring-up, cross-organizational technical leadership, agentic AI workflow construction
Preferred skills
silicon photonics, BER-bathtub extrapolation, on-die calibration verification, JEDEC participation
Technologies
VNA, TDR, switch-matrix automation, pattern generators, AI-assisted development pipelines
Responsibilities
Derive electrical characterization plans from architecture specifications, author observability and test-access requirements, develop automated data acquisition frameworks, measure and calibrate characterization hardware, serve as expert on link/timing integrity and first-silicon bring-up, co-author sim-to-silicon correlation reports, sign tape-out readiness items, define bench capability roadmaps, architect AI-enabled characterization pipelines
Seniority
Senior, hands-on IC
