Principal Engineer - HIG HBM - ARCHITECTURE
Core
Define and drive the architecture of high-speed analog and mixed-signal IO subsystems for next-generation High Bandwidth Memory (HBM) products used in AI and high-performance computing.
Role type
Principal IC Architecture Engineer (HBM PHY/IO)
Builds
High-bandwidth memory chips for AI and HPC applications
Domain
Semiconductor / Memory / High-Speed Analog & Mixed-Signal
Deliverable
production ML models | product features
Required skills
Analog and mixed-signal IO design, High-speed transmitter/receiver architecture, Clocking and timing alignment, Analog calibration schemes, Silicon learning frameworks, PPA tradeoff analysis
Preferred skills
HBM/DDR/UCIe/PCIe experience, Advanced packaging (2.5D/3D/TSV), Silicon bring-up and post-silicon debug, AI-enabled analytics for design, Simulation-to-silicon correlation
Technologies
HBM, DDR, UCIe, PCIe, PLLs, TSV, 2.5D/3D integration
Responsibilities
Define next-generation HBM PHY and IO architecture, Architect high-performance transmit and receive paths, Define and optimize analog calibration architectures, Develop and maintain IO timing budgets and margin methodologies
Seniority
Principal, technical leadership & mentorship