Intern - PHY Digital Design & Automation Engineer, HBM
Core
Develop digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next-generation HBM PHY and IO subsystems.
Role type
Senior or Graduate Engineering Intern, Digital Design & Automation
Builds
Digital design methodologies, automation frameworks, timing analysis flows, architecture validation solutions for HBM PHY/IO
Domain
Semiconductor, High-Bandwidth Memory (HBM), Digital Design, VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital design concepts (FSMs, pipelining, CDC, timing analysis), RTL design (Verilog/SystemVerilog), Python, C++, Linux development
Preferred skills
Static timing analysis (STA), timing closure, UVM verification, EDA tools (Cadence/Synopsys/Siemens), AI/LLM workflows
Technologies
Verilog, SystemVerilog, UVM, Python, C++, Linux, Cadence, Synopsys, Siemens
Responsibilities
Support digital design, integration, and timing analysis for HBM PHY/IO; Develop verification solutions using Verilog/SystemVerilog and UVM; Create Python-based automation tools leveraging LLMs; Collaborate with architecture and verification teams; Document technical findings and present results
Seniority
Intern (Graduate/Senior level)
