Intern - HBM SoC RTL Design Engineer
Core
Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die, integrating IP and collaborating with architecture and verification teams.
Role type
Intern RTL Design Engineer (HBM SoC)
Builds
Next-generation HBM SoC logic die
Domain
Semiconductor / Memory / SoC Design
Deliverable
production ML models
Required skills
SystemVerilog, Verilog, SoC integration methodologies, RTL-to-GDS flow, synthesis, static timing analysis, EDA tools (Cadence, Synopsys, Siemens), Python/TCL/Perl/shell scripting
Preferred skills
HBM/DRAM design experience, high-speed interfaces, clocking strategies, reset architectures, power management, Agentic AI
Technologies
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell scripting
Responsibilities
Design and implement RTL for SoC-level blocks and subsystems; Integrate internal and third-party IP; Collaborate with SoC architects to translate specifications into RTL; Participate in SoC-level integration activities including clocking and power intent; Assist with pre-silicon validation and post-silicon bring-up; Contribute to design documentation and reviews; Collaborate with Product Engineering and Manufacturing teams
Seniority
Intern
