Senior Engineer, FECOS cPIE Process Integration (Loop Integration)
Core
Own process loop performance and structural optimization for critical semiconductor manufacturing modules (FEOL, MOL, CAP, BEOL, Uniformity, Backside) to drive yield improvement and technology integration.
Role type
Senior IC process integration engineer (semiconductor manufacturing)
Builds
Advanced DRAM and HBM manufacturing processes and technology ramps
Domain
Semiconductor manufacturing (DRAM, HBM)
Deliverable
production ML models | product features
Required skills
Semiconductor process integration, yield improvement, defect reduction, failure analysis, process optimization, root cause analysis, process characterization, technology ramp execution, cross-functional collaboration, advanced analytics, AI tools application
Preferred skills
Master's/PhD in EE/Materials Science/Physics/Chemical Engineering, leading yield initiatives, process conversions, monitoring strategy development, multi-site standardization
Technologies
Inline monitoring systems, electrical/defect/physical analysis tools, AI/ML platforms, automation frameworks
Responsibilities
Drive process loop performance and structural optimization; Analyze process interactions to improve yield and reliability; Lead root cause investigations using multi-modal data; Establish baseline performance and optimize process capability; Develop integration solutions for technology ramp; Collaborate with multi-functional teams to resolve challenges; Support NPI transfers and qualification activities; Define loop health indicators and monitoring plans; Develop Best Known Methods and technical standards; Apply AI and advanced analytics to enhance engineering efficiency.
