Package Pathfinding Architect, MTS
Core
Define next-generation package pathfinding and system architectures for complex memory systems, optimizing speed, bandwidth, power, capacity, and thermal/mechanical performance for datacenter to edge-AI platforms.
Role type
Senior IC packaging architect (memory systems)
Builds
Scalable next-generation memory packaging technologies and system architectures
Domain
Semiconductor industry, memory systems, electronic packaging
Deliverable
production ML models | product features
Required skills
Memory systems package design, signaling and IO design, PDN design, memory timing analysis, electrical simulations, EDA tool proficiency, AI/LLM application for engineering efficiency
Preferred skills
PhD in technical field, signal and power integrity analysis, mechanical and reliability analysis, thermal analysis, memory systems architecture expertise
Technologies
Ansys, Siemens, Cadence, JMP, Python, MATLAB
Responsibilities
Lead cross-stack co-optimization across silicon, package, board, and system; Drive long-term memory technology packaging strategy; Interface between package process technology, materials, electrical, thermo-mechanical, and system performance areas; Develop AI-based EDA and automation tool sets; Partner with customers to build innovative ideas into scalable products
Seniority
Senior, hands-on IC