Principal Engineer – ASIC SoC Design
Core
Drive IP, Subsystem, and SoC development for next-generation memory and storage products, focusing on micro-architecture, RTL design, and end-to-end SoC execution.
Role type
Principal Engineer – ASIC SoC Design
Builds
Next-generation memory and storage products (DRAM, NAND, NOR)
Domain
Semiconductor / Memory and Storage
Deliverable
production ML models | product features
Required skills
Micro-architecture, Verilog/System Verilog, RTL integration, Asynchronous design, CDC methodologies, SoC design flows (Lint, CDC, Synthesis/STA, Power), Digital design fundamentals, Scripting languages
Preferred skills
LPDDR Subsystem design, CPU Subsystems, SoC Test Controller design, ASIC controllers for storage/memory, Post-silicon debug, Silicon support
Technologies
Verilog, System Verilog, Lint, CDC, Synthesis, STA, Power analysis tools
Responsibilities
Own end-to-end IP and SoC development from micro-architecture through RTL compose and integration; Drive SoC integration including CDC, lint, synthesis, STA, and power analysis; Define and review module interfaces and system-level architecture; Support post-silicon debug and bring-up activities; Provide technical mentorship and participate in design reviews
Seniority
Principal, hands-on IC with mentorship
