Principal Layout Designer, Next-generation HBM Architecture
Core
Design layouts for critical analog and mixed-signal blocks in next-generation 3D-stacked high-bandwidth memory architectures.
Role type
Principal IC Layout Designer (Analog/Mixed-Signal)
Builds
High-performance memory chips for AI systems and applications
Domain
Semiconductor / Memory / Analog & Mixed-Signal IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout fundamentals, Cadence VLE/VXL, Mentor Graphics Calibre DRC/LVS, speed/capacitance/power/area optimization, signal integrity, advanced packaging integration
Preferred skills
DRAM layout experience, 8+ years analog/mixed-signal layout experience
Technologies
Cadence VLE, Cadence VXL, Mentor Graphics Calibre
Responsibilities
Design layouts for critical analog and mixed-signal blocks; Drive exploratory layout process including floorplanning, placement, and routing; Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation; Collaborate across domains including signal integrity, architecture, design, and advanced packaging
Seniority
Principal, hands-on IC
