Staff Engineer - ASIC Test Controller Verification Lead
Core
Lead verification for ASIC Test Controllers and MBIST within SoC architectures, developing UVM-based testbenches and automation flows to enable functional characterization in silicon.
Role type
Staff Engineer - ASIC Test Controller Verification Lead
Builds
Production verification environments and test vectors for memory/storage SoCs
Domain
Semiconductor / ASIC Design / Memory & Storage
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, SoC Architecture, Test Controller Architecture, MBIST, DFT, ATE/Functional Characterization, Python, Perl, TCL, Constrained Random Testing, Debugging
Preferred skills
PCIE, LPDDR, ONFI/NAND interfaces
Technologies
UVM, SystemVerilog, Python, Perl, TCL
Responsibilities
Create SoC Verification plan and develop C/SV/UVM based SoC verification tests; Develop SV/UVM monitors to measure performance and improve Verification Environment; Interact with Architecture/Design/Tester teams to identify ASIC test vectors and functional patterns requirement; Develop flows to automate verification environment development and drive team; Involve in Vectors Bring-up activity and support ATE/Tester teams for Functional Characterization
Seniority
Staff, hands-on IC with mentorship
