SOC Formal Verification Engineer, HBM
Core
Ensuring functional correctness of complex system-on-chip and intellectual property designs using formal verification methods.
Role type
Formal Verification Engineer (Hardware/SoC)
Builds
System-on-chip (SoC) and block-level designs for memory and storage solutions
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital design fundamentals (FSM, pipelines, clocking), RTL design (Verilog/SystemVerilog), formal verification concepts (assertions, properties, proofs), debugging formal counterexamples, collaborative engineering
Preferred skills
SystemVerilog Assertions (SVA), formal verification tools (JasperGold, VC Formal, Questa Formal), low-power design (UPF/CPF), scripting (Python, TCL, shell)
Technologies
JasperGold, VC Formal, Questa Formal, Verilog, SystemVerilog, UPF, CPF, Python, TCL
Responsibilities
Debug and analyze formal counterexamples to identify root causes of functional issues in RTL designs; Collaborate with RTL designers and architects to resolve bugs; Support block-level and subsystem-level formal verification; Contribute to verification documentation including properties, assumptions, and coverage; Participate in design and verification reviews
Seniority
Mid-level IC Engineer
