Senior Engineer, IP Dev Layout
Core
Design and development of critical analog, mixed-signal, custom digital blocks, and full chip level integration support for memory and storage solutions.
Role type
Senior IC analog/mixed-signal layout engineer
Builds
Block-level layouts and full chip integrations for DRAM, NAND, and NOR memory products
Domain
Semiconductor manufacturing / VLSI design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout fundamentals (matching, electromigration, latch-up, coupling, crosstalk, IR-drop), Cadence VLE/VXL, Mentor Calibre DRC/LVS, advanced CMOS process knowledge (Planar, FinFET), circuit-aware layout (speed, capacitance, power, area), build constraints and hierarchy understanding, physical verification problem-solving
Preferred skills
Multiple tape-out support experience, AI tool exploration for daily tasks
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and develop critical analog, mixed-signal, custom digital blocks and full chip level integration; Perform layout verification (LVS/DRC/Antenna) and quality checks; Deliver block-level layouts on time with acceptable quality; Plan, estimate area/time, schedule, and execute projects; Support project management and communicate with global engineering teams
Seniority
Senior, hands-on IC
