DRAM Design Technology Layout Engineer
Core
Translating schematics into layout for DRAM fabrication reticules and developing IP layouts for DRAM chips.
Role type
DRAM Design Technology Layout Engineer
Builds
Fabrication reticules and DRAM chip IP layouts
Domain
Semiconductor manufacturing / DRAM memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Advanced CMOS layout design, Physical verification (LVS/DRC/EM), Layout area and routing optimization, Design rule compliance, Yield and reliability analysis, Schematic understanding, CAD team collaboration, Parasitic analysis, Electro-migration and IR-drop analysis, Cadence Virtuoso tools, Mentor Calibre tools
Preferred skills
Layout automation scripting, Multi-tasking
Technologies
Cadence Virtuoso, Mentor Calibre
Responsibilities
Develop IP layouts for DRAM chips, Perform layout verification (LVS/DRC/EM), Ensure on-time delivery of block-level layouts, Plan and detail layouts for global team review, Connect with global engineering teams to ensure project success
Seniority
Mid-level, hands-on IC