Memory Design Engineer
Core
Develop and optimize advanced memory bitcells, array architectures, and peripheral circuits for high-performance, high-density, low-power embedded memory on Intel's advanced CMOS process technologies.
Role type
Senior IC memory design engineer
Builds
Memory IP, test chips, and PDK libraries for Intel's advanced process technologies
Domain
Semiconductor manufacturing / Memory technology / Analog circuit design
Required skills
Memory bitcell and circuit design, Array architecture design, Peripheral circuit design, Design-technology co-optimization (DTCO), PDK enablement, Test chip execution and validation, EDA tools (Cadence Virtuoso, Synopsys StarRC, Synopsys HSPICE), Simulation, Layout design, Verification
Preferred skills
Advanced CMOS process technologies knowledge, Device physics, Power-performance-area (PPA) trade-off optimization, Custom memory circuit design (SRAM, register files, ROM), Physical design optimization
Technologies
Cadence Virtuoso, Synopsys StarRC, Synopsys HSPICE
Responsibilities
Define and optimize memory bitcells and array architectures, Lead memory pathfinding and PPA optimization via DTCO, Develop and validate memory libraries for PDK enablement, Design memory arrays and IP and execute test chips
Seniority
Senior, hands-on IC
