SoC Validation Engineer – Power Management
Core
Validate power management architectures and features for Intel's next-generation SoC designs to ensure design quality, functionality, and power efficiency.
Role type
Senior IC SoC Validation Engineer (Power Management)
Builds
Next-generation Intel silicon products for data center and computing infrastructure
Domain
Semiconductor / SoC Design / Power Management
Required skills
SystemVerilog, UVM, pre-silicon validation, functional validation, silicon validation, digital design fundamentals, computer architecture, SoC design concepts, simulation, emulation, debugging, root-cause analysis, Python/Perl/Shell scripting
Preferred skills
Power management architecture validation, DVFS, power gating, clock gating, low-power state management, reset validation, telemetry feature validation, assertion-based verification, formal verification, AI-assisted validation, technical leadership
Technologies
SystemVerilog, UVM, Python, Perl, Shell, Simulation platforms, Emulation platforms
Responsibilities
Develop and execute comprehensive validation plans for power management features; Design, develop, and maintain validation environments, automated test content, and debug infrastructure; Validate critical power management features including DVFS, power gating, clock gating, low-power states, reset flows, thermal management, and telemetry; Execute simulation and emulation workloads to identify design issues; Analyze validation results, coverage metrics, and performance data; Drive root cause analysis and debug of complex design issues; Develop and maintain automation frameworks and regression environments; Review architecture specifications to assess validation impact; Mentor junior engineers on validation and debug challenges
Seniority
Senior, hands-on IC with mentorship responsibilities
