GPU IP Lead Emulation Model Build Engineer
Core
Builds functional emulation model environments using graphics logic components (3D graphics, media) for various media IPs and maintains verification infrastructure.
Role type
Senior IC emulation model build engineer
Builds
Functional emulation models and verification infrastructure for media IP/SoC
Domain
Semiconductor hardware verification (pre-silicon emulation)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Emulation model build and release, emulation platform usage (ZeBu, Palladium, Veloce, FPGA), emulation software suites (Maestro, Metro-Maestro, Supercollider), RTL verification, FW-HW co-verification, performance validation, test environment design, IP test environment architecture (checkers, monitors, VC), digital design fundamentals (FSM, registers, counters), validation processes (HSD-ES, DCCB, Gatekeeper), scripting (Python, Perl, Ruby), problem-solving and debugging
Preferred skills
Media industry trends and technologies
Technologies
ZeBu, Palladium, Veloce, FPGA, Maestro, Metro-Maestro, Supercollider, Verdi, VCS, UVM/OVM
Responsibilities
Standalone drives and builds functional emulation model environment, maintains and improves existing functional verification infrastructure, participates in definition of verification infrastructure and TFMs, works with EDA vendors to enhance emulation model builds, designs and optimizes test environments and stress stimuli, architects IP test environments, identifies and diagnoses problems to propose and implement solutions
Seniority
Senior, hands-on IC
