Senior IP Architect – Unified Intel Chassis (UIC) IP and Platform Architecture
Core
Define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems, ensuring implementation-aware, scalable, and power-optimized designs.
Role type
Senior IC SoC IP Architect (Interconnect & Subsystems)
Builds
UIC Coherent/Non-Coherent Fabric, Protocol Adaptors (AXI, CHI, CXL, UAL), Cache Controller, MMU/IOMMU, Clock/Reset/Power Management, Debug/Analytics, Security IP
Domain
Semiconductor / SoC Design / Interconnect Architecture
Deliverable
production ML models | product features
Required skills
SoC IP architecture, AMBA protocols (AXI, CHI, APB), arbitration and routing algorithms, end-to-end QoS, high-bandwidth low latency design, platform performance modelling (IP to SoC level), architecture trade-off analysis, spec2silicon tooling
Preferred skills
fabric-based scalable platforms, performance modelling (SystemC/TLM/UVM), security architecture, cache architecture, memory management
Technologies
SystemC, TLM, UVM, AXI, CHI, CXL, UAL
Responsibilities
Author architecture specifications for UIC IP components and subsystem integration; Drive platform performance analysis and closure including bottleneck identification; Build and enhance platform performance environments and benchmarking flows; Define and validate QoS, arbitration, and routing strategies; Partner with system architects, RTL, verification, and firmware teams; Define architecture trade-offs, interfaces, and success criteria
Seniority
Senior, hands-on IC
