Back-End TD Reliability Lab Manager
Core
Lead a team of 7-10 engineers to manage stress test and reliability laboratories for next-generation semiconductor packaging technologies.
Role type
Senior IC laboratory manager (semiconductor reliability)
Builds
Reliability test capabilities and qualification data for advanced packaging (HBI, EMIB, Foveros)
Domain
Semiconductor manufacturing / Advanced packaging / Reliability engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Engineering leadership, process qualification, reliability risk assessment, quality management systems, stress testing, 8D/root cause analysis
Preferred skills
Reliability statistics and life prediction, accelerated life testing (ALT), dynamics testing (shock/vibration), JEDEC standards, JESD47, advanced packaging assembly processes, third-party lab auditing
Technologies
JEDEC standards, JESD47, ALT, AQL/SQL
Responsibilities
Manage and develop a high-performing team of 8-10 laboratory engineers; Define and execute the laboratory capability and capacity roadmap; Ensure timely response to internal and external customer needs; Develop strategies for data collection and qualification of emerging packaging technologies; Establish and advance Reliability Quick Turn Monitoring (QTM) methodologies; Drive operational excellence and continuous improvement; Lead quality management system development for ISO 17025 accreditation
