Senior EDA Tools Software Engineer
Core
Design and build a new chassis automation tool that translates SoC architectural requirements into generated RTL, register definitions, and verification collateral for non-compute infrastructure.
Role type
Senior IC EDA tooling engineer (SoC chassis automation)
Builds
A configurable, parameterized automation framework for generating SoC chassis components (interconnects, power, security, debug)
Domain
Semiconductor design automation / SoC development
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Python, System Verilog, JSON/YAML schema design, SoC architecture concepts, RTL hierarchy, code generation frameworks, CI/CD practices
Preferred skills
Network-on-Chip (NoC) architectures, IP-XACT standards, graph-based algorithms, GUI development, industry EDA tool flows
Technologies
Python, System Verilog, JSON, YAML, Git, CI/CD
Responsibilities
Architect and implement a new chassis automation tool; analyze SoC requirements to generate RTL and verification artifacts; integrate tool flows with frontend/backend validation; enable PPA optimization loops; mentor junior engineers; drive end-to-end execution from concept to deployment
Seniority
Senior, hands-on IC with mentorship responsibilities
