Soc Subsystem Architect - AI platform Development
Core
Architecting and implementing complex SoC IP blocks for AI applications ranging from edge devices to data center accelerators.
Role type
Senior IC SoC Subsystem Architect
Builds
Fully verified, synthesis- and timing-clean SoC designs and IP blocks for AI hardware
Domain
Semiconductor / AI Hardware / SoC Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL design (Verilog/SystemVerilog), SoC system integration, multicore CPU subsystem design, standard bus protocols (AXI, AHB), high-speed and low-power design techniques, scripting (Python, TCL), EDA tools (VCS, Questa, Spyglass, Vivado, Quartus II)
Preferred skills
Clock domain crossing resolution, power optimization, timing closure, silicon bring-up and post-silicon validation, design methodology mentorship
Technologies
Verilog, SystemVerilog, Python, TCL, VCS, Questa, Spyglass, Xilinx Vivado, Altera Quartus II, AXI, AHB
Responsibilities
Lead evaluation of architectural trade-offs for features, performance, power, and system limitations; Define and document micro-architecture for complex SoC IP blocks; Collaborate with verification teams for comprehensive coverage; Develop and maintain timing constraints; Drive silicon bring-up and post-silicon validation; Mentor junior engineers on design methodology
Seniority
Senior, hands-on IC
