Memory Electrical Validation Engineer
Core
Define and execute electrical validation strategies for memory IO interfaces in mobile and desktop CPU products, ensuring signal integrity, system-level margin, and production reliability.
Role type
Senior IC memory electrical validation engineer
Builds
High-performing memory solutions for Intel CPU products
Domain
Semiconductor / Memory Interfaces / Electrical Engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (validation infrastructure & systems margin analysis)
Required skills
Memory electrical validation, signal integrity (SIV), signal margin validation (SMV), analog and mixed signal fundamentals, electrical calibration methodology, memory validation/debug processes, DOEs (Design of Experiments), root cause analysis, MRC (Memory Reference Code) requirements
Preferred skills
High-speed mixed signal design, high-speed IO electrical validation, signal integrity analysis, DDR5 and LP5 memory technologies, MRC FW components knowledge, technical leadership
Technologies
DDR5, LP5, MRC FW
Responsibilities
Define electrical validation strategies for memory IO interfaces; Validate circuit analog performance and electrical signal integrity compliance; Develop and optimize Memory Reference Code (MRC) requirements; Design and execute validation procedures and systems margin analysis; Debug electrical design features and resolve functional failures; Drive DOEs to root cause with circuit and logic design teams; Test interactions between electrical design elements; Collaborate with architecture and pre-silicon verification teams
Seniority
Senior, hands-on IC
