Senior Formal Verification Engineer – AI SoC Development
Core
Ensuring functional correctness of complex digital designs for AI SoCs using advanced formal methods.
Role type
Senior IC formal verification engineer (ASIC/SoC)
Builds
Next-generation ASICs for AI applications across edge and cloud
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features
Required skills
SystemVerilog Assertions (SVA), formal verification tools (JasperGold, VC Formal, Questa Formal), digital design concepts, clock domain crossings, low-power design, UVM-based simulation, Python/TCL/Perl scripting
Preferred skills
Leading projects, cross-functional collaboration, delivering under tight schedules, analytical skills, attention to detail
Technologies
JasperGold, VC Formal, Questa Formal, SystemVerilog, UVM, Python, TCL, Perl
Responsibilities
Own formal verification strategy and execution for SoC IP blocks; Develop and maintain formal verification environments; Write and review formal properties, constraints, and coverage goals; Collaborate with design teams to identify corner cases; Drive formal sign-off and coverage closure; Mentor junior engineers and establish best practices; Define scalable verification plans; Execute verification plans and run emulation/simulation models; Debug and root-cause issues in presilicon environment; Incorporate security verification activities; Maintain functional verification infrastructure
Seniority
Senior, hands-on IC with mentorship
