Manager ASIC Digital Design
Core
Lead development of next-generation RISC-V processor and interconnect subsystems, driving verification strategy and delivering high-performance CPU IP solutions.
Role type
Manager ASIC Digital Design (Processor/Interconnect)
Builds
RISC-V processor and interconnect subsystems
Domain
Semiconductor / CPU Design / Verification
Deliverable
production ML models | product features
Required skills
ASIC design/verification, UVM, SystemVerilog, RISC-V architecture, interconnect knowledge, simulation tools (VCS/Questa), team leadership
Technologies
UVM, SystemVerilog, VCS, Questa
Responsibilities
Lead and manage ASIC design and verification teams, Define and drive UVM-based verification strategy and coverage closure, Deliver complex CPU/IP verification programs, Collaborate with global architecture, RTL, modeling, and software teams, Establish engineering processes and best practices, Mentor and develop team members
Seniority
Manager, hands-on IC with leadership