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Quantum Bump Integration Engineer

Essex Junction💼 Full-time💰 $98,000–$98,000🗓 2026-05-19 → 2026-07-30

Core

Drive next-generation interconnect scaling and develop/integrate cryogenic, superconducting bumping processes for scalable quantum hardware packaging.

Role type

R&D bump process engineer (quantum advanced packaging)

Builds

Cryogenic-compatible bump interconnect technologies (indium, SnAg, Cu pillar, superconducting metals) for 2.5D/3D architectures

Domain

Semiconductor manufacturing / Quantum computing / Advanced Packaging

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

BEOL processes and integration, bump/wafer finish integration, wafer test/probe, OSAT collaboration, package development & assembly, Design of Experiment (DOE), statistical analysis, root-cause analysis, cryogenic system characterization, failure mode analysis, yield improvement strategies

Preferred skills

Project management, innovation in ambiguous environments, technical leadership, mentoring

Technologies

Indium, SnAg, Cu pillar, superconducting metals, TSVs, interposers, plating, litho, CMP, bonding

Responsibilities

Lead development of cryogenic-compatible bump interconnect technologies; Define and optimize bump structures, metallurgy, and process flows; Establish process windows for electrical, thermal, and mechanical stability at mK–K temperatures; Own end-to-end bump integration flows from wafer-level processing through assembly and qualification; Drive alignment between unit processes and system-level packaging requirements; Enable rapid prototyping and support transition from R&D to pilot/high-volume manufacturing; Identify and analyze failure modes; Collaborate with test teams to characterize interconnect behavior at cryogenic temperatures; Scout and evaluate new materials, processes, and integration concepts; Support co-design of package + qubit + control electronics integration; Generate process documentation, specs, and integration guidelines

Seniority

Senior, hands-on IC with R&D focus

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