SMTS Process Module Engineer - Advanced Packaging Program (2.5D and 3D Heterogeneous Integration)
Core
Developing, optimizing, and qualifying advanced packaging processes (Bond/Debond, Plasma, UV, Cleaning, Die Reconstitution, Annealing, TSV) for multi-stack wafer bonding and Die-to-Wafer integration at wafer and frame-form-carrier levels.
Role type
Senior IC process engineer (advanced packaging)
Builds
Advanced packaging processes for multi-stack wafer bonding and Die-to-Wafer integration
Domain
Semiconductor manufacturing / Advanced Packaging
Required skills
DOE techniques, statistical process control, root cause analysis, equipment qualification, process transfer, yield improvement, cost reduction, lean manufacturing, Six Sigma, cross-module project coordination
Preferred skills
Coaching and developing engineers, CIP program facilitation, safety and EHS compliance
Technologies
300mm wafer processing, Through-Silicon Via (TSV), Die-to-Wafer (D2W), Wafer-to-Wafer (W2W), Si interposer, Bond/Debond, Plasma, UV, Annealing
Responsibilities
Designing and executing experiments to develop advanced packaging etch processes; Startup and qualify new process and equipment; Improve process robustness using statistical tools and DOE; Resolve complex technical issues in own Module or yield; Support Integration and Quality organizations; Sustain and improve process/SPC; Coach and develop other engineers; Facilitate CIP programs to optimize process window, cost, yield, and productivity
Seniority
Senior, hands-on IC