Sr Engineer Design Enablement Methodology
Core
EMIR methodology engineer to identify IR drop and electromigration issues in semiconductor design flows.
Role type
Senior IC design enablement engineer (EMIR methodology)
Builds
Semiconductor design flows and automation scripts for IR drop and electromigration analysis
Domain
Semiconductor manufacturing (350nm to 12nm), analog design, EDA flows
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EMIR methodology, IR drop analysis, electromigration analysis, Perl scripting, Tcl scripting, Skill scripting, Python scripting, EDA flows, DRC, LVS, PEX, Unix environment, analog design background
Preferred skills
Java coding, genAI interest, project management, innovation in solutions
Technologies
Perl, Tcl, Skill, Python, Unix, EDA tools
Responsibilities
Develop automation scripts in Perl, Tcl, Skill, and Python; partner with EDA vendors and internal PDK teams; work with cross-functional teams to understand requirements and communicate resolutions; specify and scope methodology work items; mentor junior colleagues
Seniority
Senior, technically leading teams
