Sr FPGA Design Engineer (NetSec)
Core
Design high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for next-generation firewalls.
Role type
Senior IC FPGA Design Engineer (NetSec)
Builds
High-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for next-generation firewalls
Domain
Cybersecurity hardware / FPGA design
Required skills
SystemVerilog, Verilog RTL, FPGA synthesis, placement, routing, static timing analysis (STA), Python, C/C++, Perl, bash, high-speed IP integration, FPGA rapid prototyping, in-system logic debugging, resource optimization
Preferred skills
ASIC-to-FPGA prototyping flows, high-density FPGA platforms, formal verification, networking protocols (Ethernet, IPsec)
Technologies
Vivado, Quartus, Synopsys, AMD/Xilinx, Altera/Intel, PCIe, Ethernet, QDMA, DDR/LPDDR
Responsibilities
Write micro-architecture and functional specifications for FPGA/CPLD designs; Design SystemVerilog/Verilog RTL meeting timing, power, and area targets; Synthesize and implement designs achieving multi-clock timing closure; Prototype and validate ASIC designs on FPGA platforms; Collaborate with software and platform teams to define interfaces and integrate IP blocks; Pilot AI-driven design or verification flows
Seniority
Senior, hands-on IC
