Junior Digital Design Engineer
Core
Designing flash memory IP cores from architecture definition through RTL implementation, simulation, and tape-out for Samsung's next-generation memory products.
Role type
Junior Digital Design Engineer (VLSI/RTL)
Builds
Flash memory IP cores (SSD, eMMC/UFS)
Domain
Semiconductor / Memory / VLSI
Required skills
RTL design, VLSI micro-architecture, Python scripting, Linux/Unix environments, sign-off tools (timing, area, power), simulation and debugging
Preferred skills
None stated
Technologies
None stated
Responsibilities
Design IPs from early stages of architecture definition, through RTL implementation all the way to tape-out; Plan and define micro-architecture; Implement RTL; Simulate and debug RTL; Run sign-off tools to improve design quality (timing, area, power) (via careerplan.io/jobs/D4-005-D2-37D-junior-digital-design-engineer-at-samsung-research-and-development-center-israel)
Seniority
Junior, hands-on IC
