Junior Digital Design Engineer
Core
Designing flash memory IP from architecture definition through RTL implementation to tape-out for Samsung's next-generation memory platforms.
Role type
Junior Digital Design Engineer (VLSI/RTL)
Builds
Flash memory IPs (SSD, eMMC/UFS) and system architectures
Domain
Semiconductor memory (Flash, SSD, eMMC/UFS)
Required skills
VLSI micro-architecture design, RTL coding, RTL simulation and debugging, sign-off tool usage (timing, area, power), Python scripting, Linux/Unix environment proficiency
Preferred skills
Experience with emerging memory products, knowledge of signal processing or error correction codes
Technologies
RTL, Python, Linux/Unix, sign-off tools
Responsibilities
Plan and define micro-architecture, Implement RTL, Simulate and debug RTL, Run sign-off tools to improve design quality (via careerplan.io/jobs/D4-005-D2-37D-junior-digital-design-engineer)
Seniority
Junior, hands-on IC
