Functional Verification Engineer
Core
Develop and execute comprehensive testbenches to verify the functional correctness and protocol compliance of USB digital designs at the block and system level.
Role type
Senior IC USB Verification Engineer
Builds
USB PHY, host, device, and dual-role controller IP for connectivity products
Domain
Hardware/Connectivity IP (USB 2.0, 3.x, USB4, USB-C, Thunderbolt)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SoC Verification, USB Protocol Standards (2.0/3.2/4/USB4/USB-C/Alt Modes), UVM, SystemVerilog, VHDL, Assertion-based Verification (SVA), Regression Infrastructure, Post-silicon Bring-up, Signal Integrity Analysis, Python/Perl Scripting
Preferred skills
PCIe, DisplayPort, Thunderbolt, MIPI protocol exposure, SPICE/AMS simulation
Technologies
Synopsys VCS, Cadence Xcelium, Mentor Questa, Synopsys/Cadence/Aldec USB VIP, Ellisys, Teledyne LeCroy, Total Phase, Git, Perforce
Responsibilities
Develop and maintain UVM-based testbenches for USB PHY and controllers; Execute USB-IF Compliance Test Specifications (CTS); Lead post-silicon bring-up, enumeration validation, and link training debug; Perform signal integrity analysis correlating simulation with lab measurements; Drive interoperability testing with third-party devices; Debug and root-cause failures across simulation, emulation, and silicon environments; Mentor junior verification engineers.
Seniority
Senior, hands-on IC
