Core RTL/Microarchitecture Power Lead
Core
Drive power-efficient microarchitecture development for next-generation high-performance CPU cores (Ryzen/Epyc) by analyzing power consumption and optimizing design logic.
Role type
Senior IC microprocessor power architect
Builds
Next-gen Ryzen and Epyc CPU cores
Domain
Semiconductor / High-performance computing
Required skills
Low-power design techniques, Microprocessor architecture, RTL logic design, Power analysis tools (PTPX), Silicon validation, Cross-functional collaboration
Preferred skills
Verilog/System Verilog coding, Performance simulator analysis, Timing closure, Physical Design, Synthesis, Place and Route, AI/LLM tool development, Scripting (Ruby/Python/Perl/Shell)
Technologies
PTPX, Verilog, System Verilog, Python, Ruby, Perl, Shell
Responsibilities
Analyze power consumption of micro-architectural features; Collaborate with RTL and Physical Design teams to optimize power; Validate power consumption in Silicon; Develop and update power analysis tools using AI
Seniority
Senior, hands-on IC
